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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>/home/pc/work/Tang/25K/HUB75E/HUB75E/src/top.v.v<br>
/home/pc/work/Tang/25K/HUB75E/HUB75E/src/gowin_prom/gowin_prom.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.9 Beta-5</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW5A-LV25MG121NES</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW5A-25</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>A</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sun Oct 29 21:40:20 2023
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>TOP</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.34s, Elapsed time = 0h 0m 0.327s, Peak memory usage = 1060.043MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 1060.043MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 1060.043MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.004s, Elapsed time = 0h 0m 0.003s, Peak memory usage = 1060.043MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 1060.043MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 1060.043MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 1060.043MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.002s, Elapsed time = 0h 0m 0s, Peak memory usage = 1060.043MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.004s, Elapsed time = 0h 0m 0.002s, Peak memory usage = 1060.043MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 1060.043MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0.001s, Elapsed time = 0h 0m 0s, Peak memory usage = 1060.043MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 0.184s, Elapsed time = 0h 0m 0.183s, Peak memory usage = 1060.043MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.029s, Elapsed time = 0h 0m 0.029s, Peak memory usage = 1060.043MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.056s, Elapsed time = 0h 0m 0.054s, Peak memory usage = 1060.043MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 0.626s, Elapsed time = 0h 0m 0.602s, Peak memory usage = 1060.043MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>19</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>19</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>17</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>33</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>33</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>35</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>11</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>7</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>17</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>45</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>45</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>4</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbsppROM</td>
<td>4</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>83(38 LUT, 45 ALU) / 23040</td>
<td><1%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>33 / 23280</td>
<td><1%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 23280</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>33 / 23280</td>
<td><1%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>4 / 56</td>
<td>8%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>CLK_IN</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>CLK_IN_ibuf/I </td>
</tr>
<tr>
<td>clkn[0]_5</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>clkn_0_s0/Q </td>
</tr>
<tr>
<td>hubif/frame_clk_Z_3</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>hubif/frame_clk_s1/Q </td>
</tr>
<tr>
<td>hubif/n51_6</td>
<td>Base</td>
<td>10.000</td>
<td>100.0</td>
<td>0.000</td>
<td>5.000</td>
<td> </td>
<td> </td>
<td>hubif/n51_s2/O </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>CLK_IN</td>
<td>100.0(MHz)</td>
<td>313.5(MHz)</td>
<td>5</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>hubif/frame_clk_Z_3</td>
<td>100.0(MHz)</td>
<td>505.7(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>hubif/n51_6</td>
<td>100.0(MHz)</td>
<td>330.9(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.602</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.175</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>10.778</td>
</tr>
<tr>
<td class="label">From</td>
<td>clkn_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>clkn_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>hubif/n51_6[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>CLK_IN[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>hubif/n51_6</td>
</tr>
<tr>
<td>5.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>16</td>
<td>hubif/n51_s2/O</td>
</tr>
<tr>
<td>5.175</td>
<td>0.175</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>clkn_0_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>CLK_IN</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>10.682</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>10.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>clkn_0_s0/CLK</td>
</tr>
<tr>
<td>10.835</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>clkn_0_s0</td>
</tr>
<tr>
<td>10.778</td>
<td>-0.058</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>clkn_0_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.870</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>5.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 100.000%; route: 0.000, 0.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.000, 0.000%; tC2Q: 0.175, 100.000%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 100.000%; route: 0.000, 0.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.524</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.317</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.841</td>
</tr>
<tr>
<td class="label">From</td>
<td>reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/frame_clk_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>hubif/n51_6[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>0.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.253</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>1.440</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>presetn_s1/I0</td>
</tr>
<tr>
<td>1.966</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>presetn_s1/F</td>
</tr>
<tr>
<td>2.154</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n106_s1/I3</td>
</tr>
<tr>
<td>2.416</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>n106_s1/F</td>
</tr>
<tr>
<td>2.604</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>hubif/frame_clk_s3/I0</td>
</tr>
<tr>
<td>3.130</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>hubif/frame_clk_s3/F</td>
</tr>
<tr>
<td>3.318</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>hubif/frame_clk_s1/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>hubif/n51_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>16</td>
<td>hubif/n51_s2/O</td>
</tr>
<tr>
<td>10.188</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>hubif/frame_clk_s1/CLK</td>
</tr>
<tr>
<td>10.153</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>hubif/frame_clk_s1</td>
</tr>
<tr>
<td>9.841</td>
<td>-0.311</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>hubif/frame_clk_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.683</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.315, 53.728%; route: 0.750, 30.644%; tC2Q: 0.382, 15.628%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.534</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.307</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.841</td>
</tr>
<tr>
<td class="label">From</td>
<td>reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_oe_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>hubif/n51_6[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>0.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.253</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>1.440</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>presetn_s1/I0</td>
</tr>
<tr>
<td>1.966</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>presetn_s1/F</td>
</tr>
<tr>
<td>2.154</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n106_s1/I3</td>
</tr>
<tr>
<td>2.416</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>n106_s1/F</td>
</tr>
<tr>
<td>2.604</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>hubif/hub_oe_s3/I1</td>
</tr>
<tr>
<td>3.120</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>1</td>
<td>hubif/hub_oe_s3/F</td>
</tr>
<tr>
<td>3.307</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>hubif/hub_oe_s1/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>hubif/n51_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>16</td>
<td>hubif/n51_s2/O</td>
</tr>
<tr>
<td>10.188</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>hubif/hub_oe_s1/CLK</td>
</tr>
<tr>
<td>10.153</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>hubif/hub_oe_s1</td>
</tr>
<tr>
<td>9.841</td>
<td>-0.311</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>hubif/hub_oe_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.683</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.305, 53.539%; route: 0.750, 30.769%; tC2Q: 0.382, 15.692%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.534</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.307</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.841</td>
</tr>
<tr>
<td class="label">From</td>
<td>reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_2_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>hubif/n51_6[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>0.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.253</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>1.440</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>presetn_s1/I0</td>
</tr>
<tr>
<td>1.966</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>presetn_s1/F</td>
</tr>
<tr>
<td>2.154</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n106_s1/I3</td>
</tr>
<tr>
<td>2.416</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>n106_s1/F</td>
</tr>
<tr>
<td>2.604</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>hubif/hub_addr_10_s5/I1</td>
</tr>
<tr>
<td>3.120</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>hubif/hub_addr_10_s5/F</td>
</tr>
<tr>
<td>3.307</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>hubif/hub_addr_2_s1/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>hubif/n51_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>16</td>
<td>hubif/n51_s2/O</td>
</tr>
<tr>
<td>10.188</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>hubif/hub_addr_2_s1/CLK</td>
</tr>
<tr>
<td>10.153</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>hubif/hub_addr_2_s1</td>
</tr>
<tr>
<td>9.841</td>
<td>-0.311</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>hubif/hub_addr_2_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.683</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.305, 53.539%; route: 0.750, 30.769%; tC2Q: 0.382, 15.692%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>6.534</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>3.307</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>9.841</td>
</tr>
<tr>
<td class="label">From</td>
<td>reset_cnt_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>hubif/hub_addr_3_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>CLK_IN[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>hubif/n51_6[R]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>CLK_IN</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>CLK_IN_ibuf/I</td>
</tr>
<tr>
<td>0.683</td>
<td>0.683</td>
<td>tINS</td>
<td>RR</td>
<td>8</td>
<td>CLK_IN_ibuf/O</td>
</tr>
<tr>
<td>0.870</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>reset_cnt_2_s0/CLK</td>
</tr>
<tr>
<td>1.253</td>
<td>0.382</td>
<td>tC2Q</td>
<td>RR</td>
<td>2</td>
<td>reset_cnt_2_s0/Q</td>
</tr>
<tr>
<td>1.440</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>presetn_s1/I0</td>
</tr>
<tr>
<td>1.966</td>
<td>0.526</td>
<td>tINS</td>
<td>RR</td>
<td>2</td>
<td>presetn_s1/F</td>
</tr>
<tr>
<td>2.154</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>n106_s1/I3</td>
</tr>
<tr>
<td>2.416</td>
<td>0.262</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>n106_s1/F</td>
</tr>
<tr>
<td>2.604</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>hubif/hub_addr_10_s5/I1</td>
</tr>
<tr>
<td>3.120</td>
<td>0.516</td>
<td>tINS</td>
<td>RR</td>
<td>7</td>
<td>hubif/hub_addr_10_s5/F</td>
</tr>
<tr>
<td>3.307</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>hubif/hub_addr_3_s1/CE</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>hubif/n51_6</td>
</tr>
<tr>
<td>10.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>16</td>
<td>hubif/n51_s2/O</td>
</tr>
<tr>
<td>10.188</td>
<td>0.188</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>hubif/hub_addr_3_s1/CLK</td>
</tr>
<tr>
<td>10.153</td>
<td>-0.035</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>hubif/hub_addr_3_s1</td>
</tr>
<tr>
<td>9.841</td>
<td>-0.311</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>hubif/hub_addr_3_s1</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>-0.683</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>10.000</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>4</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 1.305, 53.539%; route: 0.750, 30.769%; tC2Q: 0.382, 15.692%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.683, 78.448%; route: 0.188, 21.552%</td></tr>
</table>
<br/>
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